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toshiba confidential TC58NVG6T2FTA00 2010-12-27c 1 tentative toshiba mos digital inte grated circuit silicon gate cmos 64 gbit (8g ? 8 bit) cmos nand e 2 prom (triple-level-cell) description the TC58NVG6T2FTA00 is a single 3.3 v 64 gbit (79, 054,700,544 bits) nand electrically erasable and programmable read-only memory (nand e 2 prom) organized as (8192 ? 1024) bytes ? 258 pages ?? 4156 blocks. the device has four 9216-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 9216-byte increments. the erase operation is implemented in a single block unit (2064 kbytes ? 258 kbytes:9216 bytes x 258 pages). the TC58NVG6T2FTA00 is a serial-type memory device which utilizes the i/o pins for both address and data input/output as well as for command in puts. the erase and program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recordin g, image file memory for still cameras and other systems which require high-d ensity non-volatile memory data storage. features ? organization TC58NVG6T2FTA00 memory cell array 9216 ? 1047.1171875k ? 8 register 9216 ? 8 page size 9216 bytes block size (2064k ? 258k) bytes ? modes read, reset, auto page program, auto block erase, status read, multi page program, multi bl ock erase, multi page read ? mode control serial input/output command control ? number of valid blocks min 4000 blocks max 4156 blocks ? power supply v cc ? 2.7 v to 3.6 v ? access time cell array to register 110 ? s max serial read cycle 25 ns min ? program/erase time auto page program 2000 ? s/page typ. auto block erase 3 ms/block typ. ? operating current read (25 ns cycle) 50 ma max. program (avg.) 50ma max. erase (avg.) 50 ma max. standby 100 ? a max ? package tsop i 48-p-1220-0.50c (weight: 0.53 g typ.) ? for reliability guidance, please refer to the application notes and comments (15). 60 bit ecc for each 1k bytes is required. free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 2 pin assignment (top view) pin names i/o1 ~ i/o8 i/o port ce chip enable we write enable re read enable cle command latch enable ale address latch enable psl power on select wp write protect by/ ry ready/busy v cc power supply v ccq i/o port power supply v ss ground n.c no connection vss nc nc nc i/o8 i/o7 i/o6 i/o5 nc psl vccq v cc v ss nc vccq nc i/o4 i/o3 i/o2 i/o1 nc nc nc vss 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 vcc vss nc nc nc nc by/ry re ce nc nc v cc v ss nc nc cle ale we wp nc nc nc vss vcc u 8 u 8 TC58NVG6T2FTA00 free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 3 block diagram absolute maximum ratings symbol rating value unit v cc power supply voltage ? 0.6 to 4.6 v v in input voltage ? 0.6 to 4.6 v v i/o input /output voltage ? 0.6 v to v cc ? 0.3 v ( ? 4.6 v) v p d power dissipation 0.3 w t solder soldering temperature (10 s) 260 c t stg storage temperature ? 55 to 150 c t opr operating temperature 0 to 70 c capacitance * (ta ? 25c, f ? 1 mhz) symb0l parameter condition min max unit c in input v in ? 0 v ? 10 pf c out output v out ? 0 v ?? 10 pf * this parameter is periodically samp led and is not tested for every device. i/o control circuit status register command register column buffer column decoder data register sense amp memory cell array control circuit hv generator row address decoder logic control by/ry i/o1 v ss i/o8 ce cle ale we re by/ry row address buffer decoder to wp address register psl v cc free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 4 valid blocks * symbol parameter min typ. max unit n vb number of valid blocks 4000 ? 4156 blocks note: the device occasionally contains unus able blocks. refer to application note (11) toward the end of this document. the first block (block 0) is guaranteed to be a valid block at the time of shipment. the specification for the minimum number of valid blocks is applicable over the device lifetime. recommended dc operating conditions symbol parameter min typ. max unit v cc power supply voltage 2.7 v ? 3.6 v v v ih high level input voltage 2.7 v ? v cc ? 3.6 v 0.8 x vcc ? v cc ? 0.3 v v il low level input voltage 2.7 v ? v cc ? 3.6 v ? 0.3 * ? 0.2 x vcc v * ? 2 v (pulse width lower than 20 ns) dc characteristics (ta ? 0 to 70c, v cc ? 2.7 v to 3.6 v) symbol parameter condition min typ. max unit i il input leakage current v in ? 0 v to v cc ? ? ? 10 ? a i lo output leakage current v out ? 0 v to v cc ? ?? ? 10 ? a psl = gnd or nu ?? ? 30 ma ? i cco0 * power on reset current psl = vcc,ffh command input after power on ?? ? 30 ma ? i cco1 serial read current ce ? v il , i out ? 0 ma, tcycle ? 50 ns ? ? 50 ma i cco2 programming current ? ?? ? 50 ma i cco3 erasing current ? ? ? 50 ma i ccs standby current ce ? v cc ? 0.2 v, wp ? 0 v/v cc , psl=0v/vcc/nu ? ? 100 ? a v oh high level output voltage i oh ? ? 0.4 ma (2.7 v ? v cc ? 3.6 v) 2.4 ? ? v v ol low level output voltage i ol ? 2.1 ma (2.7 v ? v cc ? 3.6 v) ? ? 0.4 v i ol ( by/ ry ) output current of by/ry pin v ol ? 0.4 v (2.7 v ? v cc ? 3.6 v) ? 8 ? ma * refer to application note(2) for detail free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 5 ac characteristics and recommended operating conditions (ta ? 0 to 70c, v cc ? 2.7 v to 3.6 v) symbol parameter min max unit t cls cle setup time 0 ? ns t cls2 cle setup time 30 ?? ns t clh cle hold time 5 ? ns t cs ce setup time 8 ? ns t cs2 ce setup time 20 ?? ns t ch ce hold time 5 ? ns t wp write pulse width 12 ? ns t als ale setup time 0 ? ns t alh ale hold time 5 ? ns t ds data setup time 10 ? ns t dh data hold time 5 ? ns t wc write cycle time 25 ? ns t wh we high hold time 10 ? ns t whw * we high hold time from final address to first data 200 ?? ns t ww wp high to we low 100 ? ns t rw ready to we falling edge 20 ?? ns t rp read pulse width 12 ?? ns t rc read cycle time 25 ? ns t rea re access time ? 20 ns t reaid re access time for id read ? 22 ns t cr ce low to re low 10 ? ns t clr cle low to re low 10 ? ns t ar ale low to re low 10 ? ns t rhoh data output hold time from re high 25 ? ns t rloh data output hold time from re low 5 ?? ns t rhz re high to output high impedance ?? 60 ns t chz ce high to output high impedance ? 30 ns t clhz cle high to output high impedance ? 30 ? ns t reh re high hold time 10 ? ns t ir output-high-impedance-to- re falling edge 0 ? ns t rhw re high to we low 30 ? ns t whc we high to ce low 30 ? ns t whr we high to re low for data output 400 ? ns t whrs we high to re low for status & id read 180 ? ns t r1 memory cell array to starting address ? 70 ? s t r2 data cache busy in read cache (following 31h and 3fh) ? 25 ? s t r3 data cache busy in read cache (following 31h and 3fh) ? 15 ? s t wb we high to busy ? 100 ns t rst device reset time (ready/read/program/erase) ? 10/10/30/200 ? s * twhw is the time from the we rising edge of final address cycle to the we falling edge of first data cycle. free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 6 ac test conditions condition parameter 2.7 v ? v cc ? 3.6 v input level 0 v to vcc input pulse rise and fall time 3ns input comparison level vcc/2 output data comparison level vcc/2 output load c l (50 pf) ? 1 ttl note: busy to ready time depends on the pull-up resistor tied to the by/ ry pin. (refer to application note (7) toward the end of this document.) programming and erasing characteristics (ta ? 0 to 70c, v cc ? 2.7 v to 3.6 v) symbol parameter min typ. max unit notes t prog average programming time ? 2000 6000 ? s t dcbsyw1 data cache busy time in write cache (following 11h) ?? ?? 10 ?? s t dcbsyw2 data cache busy time in write cache (following 15h) ?? ?? 10000 ?? s (2) t dcbsyw3 data cache busy time in write cache (following 1ah) ?? 10 ? 6000 ?? s (3) n number of partial program cycles in the same page ? ? ? (1) t berase block erasing time ? 3 10 ms (1) refer to application note (10) toward the end of this document. (2) t dcbsyw2 depends on the timing between internal programming time and data in time. (3) in case of program operation with data cache, t dcbsyw3 depends on the timing between internal programming time and data in time. data output when treh is long, output buffers are disabled by / re=high, and the hold time of data output depend on trhoh (25 ns min). on this condition, wa veforms look like normal serial read mode. when treh is short, output buffers are not disabled by /re=high, and the hold time of data output depend on trloh (5ns min). on this condition, output buffers are disabled by the rising edge of cle, ale, /ce or falling edge of /we, and waveforms look like extended data output mode. data output can be output synchronously with the clock after 05h+address*5cycle+e0h sequence. free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 25 id read operation timing diagram : v ih or v il we cle re t cr ce ale i/o t ar id read command address 00 maker code device code t reaid t cls t cs t ds t ch t alh t als t cls t cs t ch t alh t dh 90h 00h 98h t reaid deh t reaid t reaid t reaid see table 5 see table 5 see table 5 free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 26 pin functions the device is a serial access memory which utiliz es time-sharing input of address information. command latch enable: cle the cle input signal is used to control loading of the operation mode command into the internal command register. the command is latched into the command regi ster from the i/o port on the rising edge of the we signal while cle is high. address latch enable: ale the ale signal is used to control loading address in formation into the internal address register. address information is latched into the address register from the i/o port on the rising edge of we while ale is high. chip enable: the device goes into a low-power standby mode when ce goes high during the device is in ready state. the ce signal is ignored when device is in busy state ( by/ry ? l), such as during a program or erase or read operation, and will not enter standby mode even if the ce input goes high. write enable: the we signal is used to control the acqu isition of data from the i/o port. read enable: the re signal controls serial data output. data is available t rea after the falling edge of re . the internal column address counter is also increme nted (address = address + l) on this falling edge. i/o port: i/o1 to 8 the i/o1 to 8 pins are used as a port for transferring address, command and input/ output data to and from the device. write protect: the wp signal is used to protect the de vice from accidental programming or erasing. the internal voltage regulator is reset when wp is low. this signal is usua lly used for protecting the data during the power-on/off sequence when input signals are invalid. ready/busy: the by/ry output signal is used to indicate th e operating condition of the device. the by/ry signal is in busy state ( by/ry = l) during the program, erase and read operations and will return to ready state ( by/ry = h) after completion of the operation. the output buff er for this signal is an open drain and has to be pulled-up to vcc with an appropriate resister. power on select: psl the psl signal is used to select wh ether the device initialization should take place during the device power on or during the first reset. please refer to the application note (2) for details. ce we re wp by/ry free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 27 schematic cell layout and address assignment the program operation works on page units wh ile the erase operation works on block units. a page consists of 9216 bytes in which 8192 bytes are used for main memory storage and 1024 bytes are for redundancy or for other uses. 1 page ? 9216 bytes 1 block ? 9216 bytes ? 258 pages ? (2064k ? 258k)bytes capacity ? 9216 bytes ? 258 pages ? 4156 blocks an address is read in via the i/o port over five consecutive clock cycles , as shown in table 1. table 1. addressing i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 first cycle ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second cycle l l ca13 ca12 ca11 ca10 ca9 ca8 third cycle l pa6 pa5 pa4 pa3 pa2 pa1 pa0 ca0 to ca13: column address pa0 to pa19: page address pa0 to pa6: wl address in a block pa7 to pa19: block address fourth cycle pa14 pa13 pa12 pa11 pa10 pa9 pa8 pa7 fifth cycle l l l pa19 pa18 pa17 pa16 pa15 note) (a) block address (pa7 to pa19) can only be selected between block 0 and block 4155. (b) wl address in a block (pa0 to pa6) can only be selected between wl 0 and wl 85. (c) there are lower/middle/upper address in a wl, which is selected 01/02/03h command. input of the address other than specified above is invalid. if those unspecified addresses are inpu tted in program or erase operation, th e device will output a fail status to respond to status read command. in case of read operation, some invalid data will be outputted by the device. please refer to application note (12) toward the end of this document for block management. 9216 1072248 pages 4156 blocks 8192 8192 1024 1024 page buffe r data cache i/o8 i/o1 258 pages ? 1 block 8i/o free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 28 block arrangement the device has block gaps and chip gap( s). block arrangement is as follows. block 0 block 1 4156 blocks block gap block gap block 2 block gap block gap block 4155 chip gap 00000h page address (hexadecimal) 00100h 00056h 00156h 00200h 00256h 103b00h 103b56h free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 29 operation mode: logic and command tables the operation modes such as program, erase, read and reset are controlled by command operations shown in table 3. address input, comma nd input and data input/output are controlled by the cle, ale, ce , we , re and wp signals, as shown in table 2. table 2. logic table cle ale ce we re wp * 1 psl * 3 command input h l l h * 0v/ v cc/ nu data input l l l h h 0v/ v cc/ nu address input l h l h * 0v/ v cc/ nu serial data output l l l h * 0v/ v cc/ nu during program (busy) * * * * * h 0v/ v cc/ nu during erase (busy) * * * * * h 0v/ v cc/ nu * * h * * * 0v/ v cc/ nu during read (busy) * * l h ( * 2) h ( * 2) * 0v/ v cc/ nu program, erase inhibit * * * * * l 0v/ v cc/ nu standby * * h * * 0 v/v cc 0v/ v cc/ nu h: v ih , l: v il , * : v ih or v il * 1: refer to application note (8) toward the end of this document regarding the wp signal when program or erase inhibit * 2: if ce is low during read busy, we and re must be held high to avoid unintended command/address input to the device or read to device. reset or status read command can be input during read busy. * 3: psl must be tied to either 0v or vcc, or left unconnected (nu). free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 30 table 3. command table (hex) first cycle second cycle acceptable while busy serial data input 80 ?? read 00 30 data out & column address change in serial data output 05 e0 next page read with wl address increment 31 ?? next page read w/o wl address increment 3f ?? set 1 st program mode 09 set 2 nd program mode 0d lower page select 01 middle page select 02 upper page select 03 auto page program 80 10 column address change in serial data input 85 ? auto program with data cache 80 15 multi page program 80 11 input data to page buffer 80 1a auto block erase 60 d0 id read 90 ? status read 70 ?? ? status read for multi-page program 71 ?? ? reset ff ?? ? table 4 shows the operation states for read mode,when treh is long. table 4. read mode operation states cle ale ce we re i/o1 to i/o8 power output select l l l h l data output active output deselect l l l h h high impedance active h: v ih , l: v il , hex data bit assignment (example) 1 0 0 0 0 0 0 0 8765432i/o1 serial data input: 80h free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 47 id read the device contains id codes which can be used to iden tify the device type, the ma nufacturer, and features of the device. the id codes can be read out under the following timing conditions: table 5. code table description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 1st data maker code 1 0 0 1 1 0 0 0 98h 2nd data device code 1 1 0 1 1 1 1 0 deh 3rd data chip number, cell type ? ? ? ? ? ? ? ? see table 4th data page size, block size, redundant size, organization ? ? ? ? ? ? ? ? see table 5th data extended block ? ? ? ? ? ? ? ? see table 2nd data description i/o8 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 hex data 8 gbits 1 1 0 1 0 0 1 1 d3h 16 gbits 1 1 0 1 0 1 0 1 d5h 32 gbits 1 1 0 1 0 1 1 1 d7h 64 gbits 1 1 0 1 1 1 1 0 deh 128 gbits 0 0 1 1 1 0 1 0 3ah memory density per each /ce 256 gbits 0 0 1 1 1 1 0 0 3ch 3rd data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 internal chip number per each /ce 1 2 4 8 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 reserved 0 or 1 0 0 or 1 0 or 1 90h 00h 98h deh see table 5 see table 5 see table 5 we cle re t cr ce ale i/o t ar t reaid id read command address 00 maker code device code free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 48 4th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 page size (without redundant area) 2 kb 4 kb 8 kb reserved 0 0 1 1 0 1 0 1 default value 1 0 0 block size (without redundant area) reserved 0 or 1 0 or 1 default value 0 0 0 redundant area size reserved 0 or 1 0 or 1 5th data description i/o8 i/o7 i/o 6 i/o5 i/o4 i/o3 i/o2 i/o1 plane number per each /ce 1 2 4 8 0 0 1 1 0 1 0 1 reserved 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 57 (11) invalid blocks (bad blocks) the device occasionally contains unusable blocks. therefore, the following issues must be recognized: at the time of shipment, the bad bl ock information is marked on each bad block. please do not perform an erase operation to bad blocks. it may be impossible to recover the bad block information, if the information is erased. check if the device has any bad blocks after installation into the system. refer to the test flow for bad block detection. bad blocks which are detected by the test flow must be managed as unusable blocks by the system. a bad block does not affect the perfor mance of good blocks because it is isolated from the bit lines by select gates. the number of valid blocks over th e device lifetime is as follows: min typ. max unit valid (good) block number 4000 ?? 4156 block bad block test flow regarding invalid blocks, bad block mark is in both the 1st and the last page. * 1:no erase operation is allowed to detected bad blocks. *2: bad column detection shoud be operated before detecting bad block information and bad columns should be skipped when bad block information is read. (for example) in case of column 0 or 8192 is bad column, it should be checked the next column(column 1 or 8193). bad block bad block pass read ffh check column 0 or 8192 of the first page start if fail block no ? 1 block no. ? block no. ? 1 last block end yes no read ffh check column 0 or 8192 of the last page entry bad block *1 if fail pass free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 60 package dimensions weight: 0.53 g (typ.) free datasheet http://www.datasheet.in/
toshiba confidential TC58NVG6T2FTA00 2010-12-27c 62 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software an d systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situat ions in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, cu stomers must also refer to and comply with (a) the latest ve rsions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and cond itions set forth in the "toshiba se miconductor reliability handbook" and (b) the instructions for the application with which the product will be us ed with or for. customers are solely responsible for all aspe cts of their own product design or applications , including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in c harts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operatin g parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specif ic applications as expre ssly stated in this document . product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic s ignaling equipment, equipment used to control combustions or explosions, safety devices, elevat ors and escalators, devices related to el ectric power, and equipment used in finance-related fields. do not use product for unintended use unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no re sponsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this documen t, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related soft ware or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or m anufacturing of nuclear, chemical , or biological weapons or missi le technology products (mass destruction w eapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. expor t administration regulations. ex port and re-export of product or related software or technology are strictly prohibited exc ept in compliance with all applicable export laws and regulations. ? product is subject to foreign ex change and foreign trade control laws. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result o f noncompliance with applicable laws and regulations. free datasheet http://www.datasheet.in/

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